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Virtual Addresses

Virtual Addresses

In windows this address translation is done by the MMU (Memory Management Unit)

48bit addressing: 0x00007FFFFFFFFFFF - 0xFFFF800000000000 invalid memory
56bit addressing: 0x007FFFFFFFFFFFFF - 0xFF80000000000000 invalid memory
64bit addressing: No invalid memory

64bit (48bit addressing)

The address is split into 4 9bit chunks and a 12 bit chunk (48 bits).

page_map_lvl_4[256]
page_directory_pointer_table[256]
page_directory_table[256]
page_table[256]

address = 0x00007f9bb1b21000
#|0 |000 0000 0000 0000| 0111 1111 1|001 1011 10|11 0001 101|1 0010 0001| 0000 0000 0000|
#|NX| Unused           | PML4       | PDPT      | PDT       | PT        | Page bits     |
pml4_offset = 0b0111_1111_1
pdpt_offset = 0b001_1011_10
pdt_offset =  0b11_0001_101
pt_offset =   0b1_0010_0001


bitflags = {									  # If Set info
			0b0000_0000_0001:"Valid Bit",         # This memory is not paged out
			0b0000_0000_0010:"Write Bit",         # This page be written to
			0b0000_0000_0100:"Owner Bit",         # Mem is accessible from user mode
			0b0000_0000_1000:"Write Through Bit", # Write to memory first not cache
			0b0000_0001_0000:"Cache DisabledBit", # Do not cache if set
			0b0000_0010_0000:"Accessed Bit",      # Has been accessed
			0b0000_0100_0000:"Dirty Bit",         # Has been written to
			0b0000_1000_0000:"Large Bit",         # When the page size is > 4kb
			0b0001_0000_0000:"Global Page Bit",   # Page should be flushed into the TLB cache
			0b0010_0000_0000:"Copy on Write Bit", # make a copy of the page before writing
			0b0100_0000_0000:"Prototype Bit",     # Use this page as a template for the bit flags when making other pages
			0b1000_0000_0000:"Write Bit",         # Software write bit. Used with a page fault interrupt to set dirty bit and do other operations
			}

page_bits = 0b0000 0000 0000

page_start_address = (((page_map_lvl_4[pml4_offset])[pdpt_offset])[pdt_offset])[pt_offset]

[]

  1. Page Map level 4 (PML4)
  2. Page Directory Pointer Table (PDPT)
  3. Page Directory Table (PDT)
  4. Page Table (PT)

32bit

Virtual memory serves as a key component in the architecture of contemporary operating systems, not excluding Windows. Essentially, it's an ingenious abstraction layer that empowers processes by creating an illusion of a vast, continuous memory block, despite the fact that the actual physical memory is often considerably smaller and shared among numerous processes.

At its core, virtual memory hinges on the idea of address translation, shifting from a "virtual" framework, leveraged by programs and processes, to "physical" addresses that point to concrete locations in the hardware's memory.

Virtual memory address translation
Private Virtual Space for Processes: Windows grants each process its own exclusive virtual address space. In the realm of 32-bit Windows, this typically amounts to 4GB of space (2^32 bytes). However, for 64-bit variants, the virtual address space is exponentially larger (theoretically 2^64 bytes, but practically curtailed by hardware constraints and Windows' architectural design).

Mapping Virtual Memory to Physical Memory: There isn't a direct correlation between virtual and physical memory. The operating system curates a map, dubbed a page table, that links every virtual memory address to a coinciding physical memory address.

Understanding Page Tables: A page table, housed in memory, holds an entry for every memory page a process employs. Here, a page represents a fixed memory block, usually 4KB on most systems. Each entry specifies the physical memory address where the page resides.

The Role of the Memory Management Unit (MMU): Residing within the CPU, the Memory Management Unit (MMU) shoulders the responsibility of translation. When a process seeks to access a memory location, it supplies a virtual address. The MMU, employing the page table, transposes this into a physical address. Dealing with Page Faults: In the event of a process requesting an address absent from the current page table (for instance, if the corresponding page is on the hard disk due to infrequent use), a page fault is triggered. Following this, the OS promptly loads the requisite page into physical memory and updates the page table.

Multilevel Page Tables and the TLB: Current systems employ multilevel page tables to minimize memory usage, along with a Translation Lookaside Buffer (TLB) to cache recent translations and hasten the process. Moreover, modern Windows versions harness a feature known as Physical Address Extension (PAE) to access beyond 4GB of memory.

The OS and the MMU collaborate to ensure that the virtual memory address translation process is entirely transparent to the process or program. Virtual Address Translation

Diving deep into Windows Virtual Memory, we uncover a cleverly designed system of mapping processes into their own isolated memory spaces, thereby ensuring seamless operation even in the face of limited physical memory resources. Windows Page Tables, a cornerstone of the operating system, play a pivotal role in maintaining a mapping between virtual memory addresses and their corresponding physical memory counterparts.

Shedding light on x64 Address Translation, it's a fascinating interplay of hardware and software where the Memory Management Unit (MMU) utilizes a set of page tables to translate virtual addresses into physical memory addresses. The Windows Memory Management Unit (MMU), while a largely overlooked component, is truly an unsung hero, responsible for the critical task of transforming virtual memory addresses into physical ones.

Page table translation, a mechanism in the heart of memory management, helps map virtual addresses to physical, enabling processes to operate in their own memory space. When we probe into the complexities of 64-Bit Virtual Memory Address Translation, we see that it allows Windows to manage a big address space, far beyond the confines of physical memory.

Virtual Address Translation
With 64 addressable bits on an x64 system, it's staggering to contemplate the vast 18.4 exabytes of virtual memory space available to a Windows process, an enormity that stands testament to the power of computing. A single Windows Page Table Entry, though small in size, holds information about the memory it represents, including its physical address, status, and access rights, exemplifying the beauty of this intricate system.