RISC V

RISC-V¶

Used in HDD Controllers

Registers Conventions for Linux

RV32I¶

[](https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html

• 32bit wide registers
• 32 Registers and a PC register
• Only 40 Instructions
  • LUI
  • AUIPC
  • ADDI dest_reg, src_reg, 12_bit_int
  • SLTI
  • SLTIU
  • ORI
  • ANDI
  • SLLI
  • SRLI
  • SRAI
  • ADD
  • SUB
  • SLL
  • SLT
  • SLTU
  • XOR
  • SRL
  • SRA
  • OR
  • AND
  • FENCE and FENCE.i
  • ECALL
  • EBREAK
  • BLTU
  • BGEU
  • LB
  • LH
  • LW
  • LBU
  • LHU
  • SB
  • SH
  • SW
  • JAL
  • JALR
  • BEQ
  • BNE
  • BLT
  • BGE
  • XORI

• NOP is aliased to ADDI x0, x0 0

RV32E¶

Used for embedded
- 32bit wide registers
- 16 General Purpose Registers and a PC

RV64I¶

• 64bit wide registers
• 32 General Purpose Registers and a PC
• Includes all RV32I operations and 15 new ones
  • ADDIW
  • SLLIW
  • SRLIW
  • SRAIW
  • ADDW
  • SUBW
  • SLLW
  • SRLW
  • SRAW
  • LWU
  • LD
  • SW

RV128I¶

• 128bit wide registers
• 32 General Purpose Registers and a PC